Si4420
8. Receiver FIFO Read Command
Bit
15
1
14
0
13
1
12
1
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
POR
B000h
With this command, the controller can read 8 bits from the receiver FIFO. Bit 6 (ef) must be set in Configuration Setting Command.
nSEL
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
SDI
received bits out
SDO
FFIT in RX mode / RGIT otherwise
MSB
LSB
Note: The transceiver is in receive (RX) mode when bit er is set using the Power Management Command
9. AFC Command
Bit
15
1
14
1
13
0
12
0
11
0
10
1
9
0
8
0
7
a1
6
a0
5
rl1
4
rl0
3
st
2
fi
1
oe
0
en
POR
C4F7h
Bit 7-6 ( a1 to a0 ): Automatic operation mode selector:
a1
a0
0
0
1
1
0
1
0
1
Auto mode off (Strobe is controlled by microcontroller)
Runs only once after each power-up
Keep the f offset only during receiving
Keep the f offset value
Bit 5-4 (rl1 to rl0) : Range limit. Limits the value of the frequency offset register to the next values:
rl1
0
0
1
1
rl0
0
1
0
1
Max deviation
No restriction
+15 f res to -16 f res
+7 f res to -8 f res
+3 f res to -4 f res
f res :
315, 433 MHz bands: 2.5 kHz
868 MHz band: 5 kHz
915 MHz band: 7.5 kHz
Bit 3 (st) : Strobe edge, when st goes to high, the actual latest calculated frequency error is stored into the offset register of the AFC block.
Bit 2 ( fi ):
Switches the circuit to high accuracy (fine) mode. In this case, the processing time is about twice longer, but the measurement
uncertainty is about the half.
Bit 1 ( oe ): Enables the frequency offset register. It allows the addition of the offset register to the frequency control word of the PLL.
Bit 0 ( en ): Enables the calculation of the offset frequency by the AFC circuit.
18
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